1. Field of the Invention
The present invention relates to testing apparatus and method, and more particularly relates to testing apparatus and method by providing a motherboard to test a component under test.
2. Description of the Prior Art
For the process of manufacturing integrated circuit (IC) chips, the reliability of products is a very important factor. Reliability is defined as the lifetime of a product under normal conditions. For knowing the lifetime of the products in a short time, the manufacturers usually put products to the accelerated lifetime tests to predict the average lifetime of products. The tests utilize tougher working conditions than normal, i.e. higher temperature, voltage, current, or pressure, for testing the lifetime of product in the harsh conditions and use the lifetime model to simulate the lifetime in normal conditions.
Typical reliability tests are divided into wafer-level reliability (WLR) tests and package-level reliability (PLR) tests. The WLR test apparatuses to test the wafer directly on a tester in a production line. The PLR test apparatuses to segment and package a wafer as devices-under-test (DUT), and to insert those DUTs into a DUT board to test in a high temperature oven. The stress condition of the PLR test is closer to normal working conditions of products, and the test result is more accepted by manufactures.
A typical IC PLR electric property tester is illustrated in FIG. 1, which is a schematic diagram of ap IC tester 10. The IC tester 10 contains a temperature control oven chamber 12 and a heat-resistance material 16. The thermal-resistance material 16 is fixed in the oven door 14 and cannot be moved for isolating a temperature of the temperature control oven chamber 12. The heat-resistance material 16 has some sliced crevices 18, therefore many DUT boards 13 can pass through the sliced crevices 18 to load on the oven door 14. The DUT board 13 includes a socket 19 to put a DUT 17, a testing lead 15 and a testing interface 11 to contact a DUT contacting port (not shown in this FIG). Steps of executing the IC test according to the prior art include inserting DUT 17 into sockets 19 on the DUT boards 13, loading the DUT boards 13 into sliced crevices 18 of the oven door 14, closing the oven door 14, and supplying the needed current, voltage, and high temperature conditions with the temperature control oven to perform the test.
The prior-art IC high temperature lifetime test uses a burn-in oven with functions to install patterns to increase temperature and voltage. The oven usually has bandwidth less than 250 channels, clock frequency less than 5 M HZ, and the vector memory size of stress pattern less than 128 K.
However, there are disadvantages for high pin count products (the north and south bridge chips): The prior-art oven usually has bandwidth less than 250 channels, so it does not fit the chips with many pins that it can only do stress test with some signal pins, i.e. it can only uses 1 or 2 of many patterns to be stress pattern. And the vector memory size of stress pattern is less than 128 K so the depth of stress pattern is restricted by memory size. These disadvantages result in low fault coverage rate that there are only few chances to reflect the problems of DUT. Moreover, the frequency is less than 5 M Hz and too far to practical frequency that is usually more than 100 M Hz. In the same condition of stress area and stress time, the DUT can stress 100 times with practical frequency but only does 5 times in test because limited by the oven. The disadvantage results in a very long time to reflect the problems of DUTs.
Because the chances and request time to reflect the problems of DUTs are limited by prior-art burn-in oven tester and the result of DUT test is not the same as the result of chips in practical manufactures, a new testing apparatus is needed that can reflect the problems of practical manufactures correctly in a shorter time.